The subject matter relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of improving address access time (tAA) characteristics which denote a quality factor showing how fast data are output in response to a read command, and relates to performance of the semiconductor memory device.
FIG. 1 is a block diagram of a conventional semiconductor memory device having first to eighth banks.
As a storage capacity of a semiconductor memory device increases and high performance memory devices such as a double duty rate III (DDR3) dynamic random access memory (DRAM) device are employed, semiconductor memory devices have changed from a four-bank structure to an eight-bank structure. In the semiconductor memory device, a part corresponding to a data input/output pad is called a “DQ PAD,” and a part corresponding to address and command input/output pads is called an “AC PAD”.
As shown, a plurality of DQ PADs are located at one side of a chip, and a plurality of AC PADs are located at another side of the chip. Herein, the first to eighth banks are distant from or close to the DQ pads according to their positions, and the first to eighth banks are also distant from or close to the AC pads according to their positions. For example, the sixth bank BANK5 and the eighth bank BANK7, grouped by a reference symbol “DQ WORST” and “CMD BEST,” are distant from the DQ PADs but close to the AC PADs. At another side of the chip, the first bank BANK0 and the third bank BANK2, grouped by a reference symbol “DQ BEST” and “CMD WORST,” are distant from the AC PADs but close to the DQ PADs.
FIG. 2 is a timing diagram illustrating a write operation of the first to eighth banks of FIG. 1.
In detail, an upper portion of the timing diagram shows a write operation of the banks grouped by “DQ WORST” and “CMD BEST” in a fast process, voltage and temperature (PVT) condition. A lower portion of the timing diagram shows a write operation of the banks grouped by “DQ BEST” and “CMD WORST” in a slow PVT condition. Herein, the fast PVT condition means a PVT condition that optimum tAA characteristics can be obtained such as a semiconductor is manufactured through an optimum process and operates on high voltage and low temperature conditions. On the contrary, the slow PVT conditions means a PVT condition wherein the semiconductor memory device operates with the worst tAA characteristics. Further, the tAA characteristics denote a quality factor showing how fast data are output in response to a read command.
Data to be written to the banks (hereinafter, referring to as “write data”) is transferred from the DQ PADs to the banks, and written to the banks in response to a bank write enable signal BWEN. The write data is written to a memory cell at a column side in response to a column selection signal YS, which is selected based on a column address. The column selection signal YS may be enabled at substantially the same time as an activation of the bank write enable signal BWEN, with a little time delay. Further, the column selection signal YS is delayed or advanced according as the bank write enable signal BWEN is advanced or delayed.
In general, since the write data transferred to the banks are intended to have the least delay time, the number of logic gates passed by the write data is designed to be minimized. The write data are merely transferred to the banks via a long metal line, e.g., a global input/output (GIO) line. The GIO line may have characteristics of a RC delay and a little variation between the fast PVT conditions and the slow PVT conditions. The GIO line is classified as a data-group transmission line, and thus the write data transferred via the GIO line are classified as a data-group signal. A time margin “tGIO” shown in FIG. 2 denotes a time difference caused GIO line characteristics on according to PVT variation.
On the contrary, the bank write enable signal BWEN and the column selection signal YS are more sensitive to the PVT conditions because they pass through a relatively large number of logic gates, e.g., a timing controlling circuit and other controllers. Such signals as the bank write enable signal BWEN and the column selection signal YS are classified as a command-group signal. A time margin “tCMD” shown in FIG. 2 denotes a time difference caused by PVT variation on the command-group signal. Herein, the time margin “tCMD” is larger than the time margin “tGIO”.
It is required that the data-group signal such as the write data reaches the banks prior to the command-group signal such as the bank write enable signal BWEN and the column selection signal YS so as to satisfy a timing margin “tMARGIN” shown in FIG. 2. However, the command-group signal sensitively varies according to the PVT conditions. In the fast PVT condition, the command-group signal may be much faster than in other conditions relatively to the data-group signal. Because of this, sometimes the timing margin “tMARGIN” can not be guaranteed. Accordingly, it is required that the command-group signal may be delayed for a predetermined time by design. In particular, for the banks grouped by “DQ WORST” and “CMD BEST” as shown in the upper portion of the timing diagram of FIG. 2, it is necessary for the command-group signal, such as the bank write enable signal BWEN and the column selection signal YS, to be delayed.
The lower portion of the timing diagram shown in FIG. 2 shows the write operation of the banks grouped by “DQ BEST” and “CMD WORST” in slow PVT conditions. In such conditions, the command-group signal such as the bank write enable signal BWEN and the column selection signal YS is very slowly transferred to the banks but the data-group signal such as the write data is transferred to the banks relatively faster than the command-group signal. This is because the data-group signal is transferred to the banks located at “DQ BEST” and is relatively insensitive to PVT conditions, while the command-group signal is transferred to the banks located at “CMD WORST” and delayed for the predetermined time by design for guaranteeing the timing margin “tMARGIN” in the fast PVT conditions.
In a read operation as well as the write operation, the column selection signal YS is enabled so that read data are transferred to the GIO line from the banks. In that case, there is a problem that the tAA is increased because the column selection signal YS is delayed as described above. The tAA characteristics relate to a quality factor showing how fast read data are output in response to a read command to thereby determine performance of the semiconductor memory device.